PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams

Authors:
Maksim Jenihhin;Jaan Raik;Anton Chepurov;Raimund Ubar
Affiliations:
Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia 12618;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia 12618;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia 12618;Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia 12618
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2009

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Abstract

This paper proposes a novel method for the simulation-based checking of assertions written in the PSL language. The method uses a system representation model called High-Level Decision Diagrams (HLDDs). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in Property Specification Language (PSL). Other contributions of the paper are a methodology for direct conversion of PSL properties to HLDD and modification of the HLDD-based simulator for assertion checking support. Experimental results show the feasibility and efficiency of the proposed approach.