Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design
Dynamic minimization of OKFDDs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
EDTC '95 Proceedings of the 1995 European conference on Design and Test
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Parallel breadth-first BDD construction
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division
Formal Methods in System Design
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
The K*BMD: A Verification Data Structure
IEEE Design & Test
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
Fast and Efficient Construction of BDDs by Reordering Based Synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An efficient finite-domain constraint solver for circuits
Proceedings of the 41st annual Design Automation Conference
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
AND/OR multi-valued decision diagrams (AOMDDs) for graphical models
Journal of Artificial Intelligence Research
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Journal of Electronic Testing: Theory and Applications
Interactive cost configuration over decision diagrams
Journal of Artificial Intelligence Research
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
| Hi-index | 0.01 |
Recently, two new data structures have been proposed in the area of Computer Aided Design (CAD), i.e. Ordered Kronecker Functional Decision Diagrams (OKFDDs) and Multiplicative Binary Moment Diagrams (*BMDs). OKFDDs are the most general ordered data structure for representing Boolean functions at the bit-level. *BMDs are especially applicable to integer valued functions. In this paper we propose a new data structure, called Kronecker Multiplicative BMDs (K*BMDs), that is a generalization of OKFDDs to the word-level. Using K*BMDs it is possible to represent functions efficiently, that have a good word-level description, since K*BMDs are a generalization of *BMDs. On the other hand they are also applicable to verification problems at the bit-level. We present experimental results to demonstrate the efficiency of our approach including a comparison of K*BMDs to several other data structures, like EVBDD, OKFDDs and *BMDs. Additionally, experiments on verification of fast multipliers, i.e. multipliers with worst case running time O(log(n)), are reported.