Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Breadth-first manipulation of SBDD of Boolean functions for vector processing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Brief Study of BDD Package Performance
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Information and Computation - Special issue: LICS'97
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a new approach to symbolic simulation with BDDs. Our method uses Reordering Based Synthesis (RBS) which allows the integration of dynamic variable ordering (even) within a single synthesis operation (e.g. an AND-operation). Thus, huge peak sizes during the construction can often be avoided, and we obtain a method that, with no penalty in runtime, is more memory efficient than traditional ITE operator based symbolic simulation. The results are confirmed by experiments on a large set of benchmarks: We give a comparison to previously published approaches and also consider some industrial benchmarks which are known to be hard to handle.