Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Adaptive variable reordering for symbolic model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Variable reordering for shared binary decision diagrams using output probabilities
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Efficient variable ordering using aBDD based sampling
Proceedings of the 37th Annual Design Automation Conference
Lazy group sifting for efficient symbolic state traversal of FSMs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
Formal Methods in System Design
The nonapproximability of OBDD minimization
Information and Computation
Heuristic Learning Based on Genetic Programming
Genetic Programming and Evolvable Machines
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The K*BMD: A Verification Data Structure
IEEE Design & Test
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Distributed Hybrid Genetic Programming for Learning Boolean Functions
PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature
Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics
Proceedings of the International Conference, 7th Fuzzy Days on Computational Intelligence, Theory and Applications
Heuristic Learning Based on Genetic Programming
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
k-Layer Straightline Crossing Minimization by Speeding Up Sifting
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Fast and Efficient Construction of BDDs by Reordering Based Synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
KNOW Why your access was denied: regulating feedback for usable security
Proceedings of the 11th ACM conference on Computer and communications security
Lower bounds for dynamic BDD reordering
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Distributed dynamic BDD reordering
Proceedings of the 43rd annual Design Automation Conference
IEEE Intelligent Systems
Minimization of multiway decision graphs for RTL verification by stochastic optimization
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Learning to order BDD variables in verification
Journal of Artificial Intelligence Research
Constraint and variable ordering heuristics for compiling configuration problems
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
A microcanonical optimization algorithm for BDD minimization problem
IEA/AIE'07 Proceedings of the 20th international conference on Industrial, engineering, and other applications of applied intelligent systems
Large program trace analysis and compression with ZDDs
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Preprocessing boolean formulae for BDDs in a probabilistic context
JELIA'10 Proceedings of the 12th European conference on Logics in artificial intelligence
Variable compression in ProbLog
LPAR'10 Proceedings of the 17th international conference on Logic for programming, artificial intelligence, and reasoning
Implicit permutation enumeration networks and binary decision diagrams reordering
Proceedings of the 48th Design Automation Conference
Genetic algorithms for the variable ordering problem of binary decision diagrams
FOGA'05 Proceedings of the 8th international conference on Foundations of Genetic Algorithms
Dynamic segregative genetic algorithm for optimizing the variable ordering of ROBDDs
Proceedings of the 14th annual conference on Genetic and evolutionary computation
International Journal of Cognitive Informatics and Natural Intelligence
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Dynamic reordering techniques have had considerable success in reducing the impact of the initial variable order on the size of decision diagrams. Sifting, in particular, has emerged as a very good compromise between low CPU time requirements and high quality of results. Sifting, however, has the absolute position of a variable as the primary objective, and only considers the relative positions of groups of variables indirectly. In this paper we propose an extension to sifting that may move groups of variables simultaneously to produce better results. Variables are aggregated by checking whether they have a strong affinity to their neighbors. (Hence the title.) Our experiments show an average improvement in size of 11%. This improvement, coupled with the greater robustness of the algorithm, more than offsets the modest increase in CPU time that is sometimes incurred.