Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Compositional instance-based learning
AAAI '94 Proceedings of the twelfth national conference on Artificial intelligence (vol. 1)
Parallel logic simulation of VLSI systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient OBDD-based boolean manipulation in CAD beyond current limits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Waiting false path analysis of sequential logic circuits for performance optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Selective sampling for nearest neighbor classifiers
AAAI '99/IAAI '99 Proceedings of the sixteenth national conference on Artificial intelligence and the eleventh Innovative applications of artificial intelligence conference innovative applications of artificial intelligence
Symbolic Model Checking
Machine Learning
Design error diagnosis in sequential circuits
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Intertwined development and formal verification of a 60/spl times/ bus model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Speeding up variable reordering of OBDDs
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Recursive Partitioning Decision Rule for Nonparametric Classification
IEEE Transactions on Computers
IEEE Transactions on Computers
Journal of Artificial Intelligence Research
Context-sensitive program analysis as database queries
Proceedings of the twenty-fourth ACM SIGMOD-SIGACT-SIGART symposium on Principles of database systems
An algebra for fine-grained integration of XACML policies
Proceedings of the 14th ACM symposium on Access control models and technologies
Data representation and efficient solution: a decision diagram approach
SFM'07 Proceedings of the 7th international conference on Formal methods for performance evaluation
Improving static variable orders via invariants
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
New metrics for static variable ordering in decision diagrams
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Computing argumentation in polynomial number of BDD operations: a preliminary report
ArgMAS'10 Proceedings of the 7th international conference on Argumentation in Multi-Agent Systems
BUNDLE: a reasoner for probabilistic ontologies
RR'13 Proceedings of the 7th international conference on Web Reasoning and Rule Systems
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The size and complexity of software and hardware systems have significantly increased in the past years. As a result, it is harder to guarantee their correct behavior. One of the most successful methods for automated verification of finite-state systems is model checking. Most of the current model-checking systems use binary decision diagrams (BDDs) for the representation of the tested model and in the verification process of its properties. Generally, BDDs allow a canonical compact representation of a boolean function (given an order of its variables). The more compact the BDD is, the better performance one gets from the verifier. However, finding an optimal order for a BDD is an NP-complete problem. Therefore, several heuristic methods based on expert knowledge have been developed for variable ordering. We propose an alternative approach in which the variable ordering algorithm gains "ordering experience" from training models and uses the learned knowledge for finding good orders. Our methodology is based on offine learning of pair precedence classifiers from training models, that is, learning which variable pair permutation is more likely to lead to a good order. For each training model, a number of training sequences are evaluated. Every training model variable pair permutation is then tagged based on its performance on the evaluated orders. The tagged permutations are then passed through a feature extractor and are given as examples to a classifier creation algorithm. Given a model for which an order is requested, the ordering algorithm consults each precedence classifier and constructs a pair precedence table which is used to create the order. Our algorithm was integrated with SMV, which is one of the most widely used verification systems. Preliminary empirical evaluation of our methodology, using real benchmark models, shows performance that is better than random ordering and is competitive with existing algorithms that use expert knowledge. We believe that in sub-domains of models (alu, caches, etc.) our system will prove even more valuable. This is because it features the ability to learn sub-domain knowledge, something that no other ordering algorithm does.