Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential redundancy identification using recursive learning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Illegal state space identification for sequential circuit test generation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Sequential Test Generation with Advanced Illegal State Search
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Learning to order BDD variables in verification
Journal of Artificial Intelligence Research
Functional broadside tests under an expanded definition of functional operation conditions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: In this paper, we first present an algorithm (FILL) which efficiently identifies a large subset of the illegal states in a synchronous sequential circuit, without assuming a global reset mechanism. A second algorithm, FUNI, finds sequentially untestable faults whose detection requires some of the illegal states computed by FlLL. Although based on binary decision diagrams (BDDs), FILL is able to process large circuits by using a new functional partitioning procedure. The incremental building of the set of illegal states guarantees that FILL mill always obtain at least a partial solution. FUNI is a direct method that identifies untestable faults without using the exhaustive search involved in automatic test generation (ATG). Experimental results show that FUNI finds a large number of untestable faults up to several orders of magnitude faster than an ATG algorithm that targeted the faults identified by FUNI, Also, many untestable faults identified by FUNI were aborted by the test generator.