Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Sequential Test Generation with Advanced Illegal State Search
Proceedings of the IEEE International Test Conference
Invalid State Identification for Sequential Circuit Test Generation
ATS '96 Proceedings of the 5th Asian Test Symposium
EDTC '95 Proceedings of the 1995 European conference on Design and Test
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Compact test sets for industrial circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testability of the Philips 80C51 Micro-controller
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
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