Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Illegal state space identification for sequential circuit test generation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test Pattern Generation with Restrictors
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ICCD '03 Proceedings of the 21st International Conference on Computer Design
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
Mining Sequential Constraints for Pseudo-Functional Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identifying invalid states for sequential circuit test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New techniques for untestable fault identification in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
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The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of manufacturing test. Pseudo-functional testing tries to resolve this problem by identifying illegal states in functional mode and avoiding them during the test pattern generation process. Existing methods, however, can only extract a small set of illegal states in the system due to various limitations. In this paper, we first show that illegal states in the system are mainly caused by multi-fanout nets in the circuit, and we develop efficient and effective heuristics to identify them. Experimental results on benchmark circuits demonstrate the effectiveness of our proposed systematic solution.