FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Deception by Design: Fooling Ourselves with Gate-level Models
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Maximizing Impossibilities for Untestable Fault Identification
Proceedings of the conference on Design, automation and test in Europe
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks
ITC '04 Proceedings of the International Test Conference on International Test Conference
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
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Transition delay tests are crucial to finding ICs with timing defects, but they can also find functionally untestable timing-related faults, thus reducing yield. This article describes an ATPG with constraints that prevent it from using the illegal states that lead to this overtesting.