On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Mining global constraints for improving bounded sequential equivalence checking
Proceedings of the 43rd annual Design Automation Conference
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This paper presents a new graph traversal based framework for sequential logic implication called GRAPH SIMP. Due to the prohibitive time and space cost, few previous work target the discovery of sequential indirect implications that span multiple time frames. By using an efficient graph data structure and incorporating a graph reduction step into the implication generation process, our approach provides an efficient support for sequential implication. Sequential logic implication has many useful applications, one of which is sequentially redundant fault identification. We show that sequential implications found by GRAPH SIMP allow us to find more sequential redundancies than previously reported. Results of testing our implication algorithm against ISCAS89 circuits show that high implication coverage is essential to identifying redundant faults.