Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
On the hardness of approximate reasoning
Artificial Intelligence
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Testing, Verification, and Diagnosis in the Presence of Unknowns
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Maximizing Impossibilities for Untestable Fault Identification
Proceedings of the conference on Design, automation and test in Europe
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Any nano-system that designers build must guarantee functional correctness. The sheer scale factor and the added layers of uncertainty in nano-systems demand revolutionary breakthroughs in system design tools and algorithms. Formal verification of nano systems, then, must be able to deal with large state spaces, together with the presence of unknowns and uncertainties. The methods described in this chapter present a suite of algorithms that can offer potential in reducing the problem complexity in verification of nano-systems.