Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
A Survey of Techniques for Formal Verification of Combinational Circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
An Approach to Verify a Large Scale System-on-a-chip Using Symbolic Model Checking
ICCD '98 Proceedings of the International Conference on Computer Design
Sequential circuit test generation using genetic techniques
Sequential circuit test generation using genetic techniques
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Efficient Sequential Test Generation Based on Logic Simulation
IEEE Design & Test
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
IEEE Transactions on Computers
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
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In this paper, we present a successful application of a simulation-based sequential Automatic Test Pattern Generation (ATPG) for safety property verification, with the target on verifying safety property of large, industrial strength, hardware designs for which current formal methods fail. Several techniques are developed to increase the effectiveness and efficiency during state exploration and justification of the test generator for verification, including (1) incorporation of a small combinational ATPG engine, (2) reset signal masking, (3) threshold-value simulation, and (4) weighted Hamming distance. Experimental results on both ISCAS89 benchmark circuits and real industry circuits have shown that this simulation-based verifier achieves better or comparable results to current state-of-the-art formal verification tools BINGO and CHAFF.