Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improvements to propositional satisfiability search algorithms
Improvements to propositional satisfiability search algorithms
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Introduction to Digital Logic Design
Introduction to Digital Logic Design
Symbolic Model Checking
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
The Temporal Semantics of Concurrent Programs
Proceedings of the International Sympoisum on Semantics of Concurrent Computation
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Analysis of ATPG and SAT algorithms for Formal Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation
ITC '04 Proceedings of the International Test Conference on International Test Conference
Proving the Correctness of Multiprocess Programs
IEEE Transactions on Software Engineering
A Novel Approach to Combine a SLS- and a DPLL-Solver for the Satisfiability Problem
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
| Hi-index | 14.98 |
We present a new logic-simulation-based algorithm on verifying safety properties of large sequential hardware designs. This algorithm explores the search space defined by partitioned internal circuit nodes. Two powerful features are proposed to increase the effectiveness during search space exploration and counterexample generation for verifying safety properties. These include 1) new search space constituted by internal nodes instead of state variables and 2) static learning on multiple nodes to further enlarge the target. These two features are integrated with the following techniques during our simulation: incorporation of a BCP (Boolean Constraint Propagation) engine for multiple nodes implication and multiple-time-frame GA (Genetic Algorithm) search. Because only logic simulation is needed in our algorithm, the computational effort is low. Experimental results on large benchmark circuits have shown that this logic-simulation-based verifier achieves significantly better results compared with existing formal verification tools and simulation-based methods.