Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
IEEE Transactions on Computers
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
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We present a study of the practical use of a simulation-based automatic test pattern generation (ATPG) for model checking in large sequential circuits. Preliminary findings show that ATPGs which gradually build and learn from the state-space has the potential to achieve the verification objective without needing the complete state-space information. The success of verifying a useful set of properties relies on the performance and capacity of ATPG. We compared an excitation-only ATPG with one that performs both excitation and propagation. Even though the excitation-only strategy suffices to justify the objective, the excitation-and-propagation ATPG achieved higher signal-justification coverages than the excitation-only counterpart. This is because excitation-only ATPG falls short in obtaining pertinent state information helpful for traversing the state space, resulting in ATPG aborting the objective. Our experiments demonstrated that incomplete but useful information learned via propagation can have significant impact on the performance of ATPG for model-checking.