Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines

Authors:
Daniel G. Saab;Jacob A. Abraham;Vivekananda M. Vedula
Affiliations:
-;-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

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Abstract

Industry is beginning to use Satisfiability (SAT)solvers extensively for formally verifying the correctnessof digital designs. In this paper we compare theperformance of SAT solvers with sequential AutomaticTest Pattern Generation (ATPG) techniques for propertyverification. Our experimental results on the ISCASbenchmarks as well as a model of the 8085 microprocessorshow that, contrary to popular belief, ATPG techniquesperform much better than SAT based verificationtechniques, especially for large designs.