Using Program Slicing in Software Maintenance
IEEE Transactions on Software Engineering
Incremental program testing using program dependence graphs
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Programmers use slices when debugging
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
A novel methodology for hierarchical test generation using functional constraint composition
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
An Analysis of ATPG and SAT algorithms for Formal Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Program Slicing for Hierarchical Test Generation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing of Digital Systems
Program Slicing for ATPG-Based Property Checking
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
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Design complexity is increasing with every technology generation, causing verification tools to require large amounts of resources. In this paper, we develop a technique to reduce the complexity of verifying digital designs described in a Hardware Description Language (HDL). For a given property to be verified, we derive an HDL executable design slice that is behaviorally equivalent to the original design. The slice is less complex than the original design and requires fewer resources for analysis by a verification tool. The slicer is implemented as a pre-processor to SMV, a SAT-based verification tool, and Formal, an ATPG-based verification tool. Experimental results on the USB2.0 IP core show that RTL slicing reduces both CPU and memory overhead for both SMV and Formal. This reduction allows the verification tools to effectively deal with complex designs.