Reducing verification overhead with RTL slicing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
The Role of Model-Based Testing
Verified Software: Theories, Tools, Experiments
Efficient Model Checking of Hardware Using Conditioned Slicing
Electronic Notes in Theoretical Computer Science (ENTCS)
| Hi-index | 0.00 |
This paper presents a novel technique for abstracting designsin order to increase the efficiency of formal propertychecking. Bounded Model Checking (BMC), using Satisfiability(SAT) techniques, are beginning to be widely usedfor checking properties of designs. Recent approaches usingsequential ATPG techniques, which harness the structuralinformation of the design, have been shown to performbetter than SAT-based BMC. However, these techniques requirean effective methodology to deal with the size of commercialdesigns. A program slicing methodology that hasbeen shown to accelerate sequential ATPG is adapted andintegrated into an ATPG-based BMC framework. Furthermore,a generalization of the ATPG-based approach, whichchecks for unbounded liveness, is also presented.