Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
An Analysis of ATPG and SAT algorithms for Formal Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Testing of Digital Systems
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Reducing verification overhead with RTL slicing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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This paper presents the ATPG performances of verifying USB2.0 IP core. Using the USB protocol and typical properties, the ATPG-based bounded model checking mechanism is revealed. Heuristics to accelerate the ATPG search are presented and their impacts are analyzed. We feel that results from this case study are applicable to serial communication circuits of the same family and can be scaled to industrial-sized circuits.