Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing verification overhead with RTL slicing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints on the module under test (MUT) in order to reduce the complexity for test generation. However, when this technique is applied to large designs, the embedded modules themselves become too complex for an ATPG tool to handle. If sub-modules within these complex modules are considered, the extraction of constraints may prove to be too tedious. In this paper, a novel methodology to extract constraints hierarchically is presented. We use synthesis tools to eliminate redundant logic during the constraint extraction process. The proposed methodology also facilitates the reuse of constraints extracted for different sub-modules at a given level of hierarchy. This technique was applied to the ALU unit of the ARM Verilog benchmark design, and the results presented show that this technique makes the constraint extraction process more useful for large designs.