Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A novel methodology for hierarchical test generation using functional constraint composition
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
On Structural vs. Functional Testing for Delay Faults
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Proceedings of the 41st annual Design Automation Conference
Pseudo-Functional Scan-based BIST for Delay Fault
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in generation of functional broadside tests using a fixed hardware structure
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of overtesting in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between overtesting prevention and test compression.