Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
PROBE: A PPSFP Simulator for Resistive Bridging Faults
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Modeling Feedback Bridging Faults With Non-Zero Resistance
ETW '03 Proceedings of the 8th IEEE European Test Workshop
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Proceedings of the Conference on Design, Automation and Test in Europe
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Test application at reduced power supply voltage (or VLVtesting) is a cost-effective way to increase the defect coverageof a test set. Resistive short defects are a major contributorto this coverage increase. Using a probabilistic model ofthese defects, we quantify the coverage impact of VLV testingfor different voltages. When considering the coverage increase,we differentiate between defects missed by the test setat nominal voltage and undetectable defects (flaws) detectedby VLV testing. In our analysis, the performance degradationof the device caused by lower power supply voltage isaccounted for. Furthermore, we describe a situation in whichdefects detected by conventional testing are missed by VLVtesting and quantify the resulting coverage loss. We reportthe numbers on the increased defect coverage, flaw coverage,and coverage loss for ISCAS circuits.