Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Optimal voltage testing for physically-based faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Stuck-At Fault: A Fault Model for the Next Millennium
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Realistic Coverages of Voltage and Current Tests
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
IEEE Transactions on Computers
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and simulation of real defects using fuzzy logic
Proceedings of the 37th Annual Design Automation Conference
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Modeling Feedback Bridging Faults with Non-Zero Resistance
Journal of Electronic Testing: Theory and Applications
Testing for Resistive Shorts in FPGA Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing: Theory and Applications
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
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In this work we develop models of resistive bridgingfaults and study the fault coverage on ISCAS85 circuits ofdifferent test sets using resistive and zero-ohm bridges atdifferent supply voltages. These results explain severalpreviously observed anomalous behaviors. In order toserve as a reference, we have developed the first resistivebridging fault ATPG, which attempts to detect themaximum possible bridging resistance at each fault site.We compare the results of the ATPG to the coverageobtained from other test sets, and coverage obtained byusing the ATPG in a clean-up mode. Results on ISCAS85circuits show that stuck-at test sets do quite well, but thatthe ATPG can still improve the coverage. We have alsofound that the loss of fault coverage is predominantly dueto undetected faults, rather than faults in which only asmall resistance is detected. This suggests that lower-costfault models can be used to obtain high resistive bridgefault coverage.