Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Proceedings of the IEEE International Test Conference
Test Strategy Sensitivity to Defect Parameters
Proceedings of the IEEE International Test Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Ground Bounce in Internal Logic Circuitry
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Optimal Conditions for Boolean and Current Detection of Floating Gate Faults
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Position Statement: Good Die in Bad Neighborhoods?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper reflects on some recent results that show thevalue of delay-fault tests on a deep sub-micron process.However, the results also suggest that untargetted testpatterns perform almost as well as those targetted on atransition fault model, despite appearing to have a muchlower fault coverage. This leads to an examination of thedefect mechanisms in deep sub-micron ICs, in particularthe relationship of crosstalk and power-rail coupling toresistive opens and resistive bridges. A number of newfault mechanisms are described. The paper shows theimportance of initialization conditions for resistive opensand the importance of noise margins with resistivebridges. These noise margin considerations throw doubtson the idea used by other authors of the "criticalresistance" of a bridge.