Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Delay-Verifiability of Combinational Circuits Based on Primitive Faults
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
T4: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IEEE Design & Test
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Pitfalls in delay fault testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Robust test generation for power supply noise induced path delay faults
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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We propose a new delay test generation technique that can take into account the impact ofthe power supply noise on the signal propagation delays. This is different from existing delay fault models and test generation techniquesthat ignore the dependence of path delays onthe applied test patterns and cannot capture theworst-case timing scenarios in deep submicrondesigns. In addition to sensitizing the fault andpropagating the fault effects to the primary outputs, our new tests also produce the worst-casepower supply noise on the nodes in the targetpath. Thus, the tests also cause the worst-casepropagation delay for the nodes along the targetpath. Our experimental results on benchmarkcircuits show that the new delay tests producesignificantly longer delays on the tested pathscompared to the tests derived using existing delay testing methods.