K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Estimation of maximum power for sequential circuits considering spurious transitions
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Dynamic Timing Analysis Considering Power Supply Noise Effects
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analyzing software influences on substrate noise: an ADC perspective
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Modeling and estimation of power supply noise using linear programming
Proceedings of the International Conference on Computer-Aided Design
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We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.