Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Gate-level current waveform simulation of CMOS integrated circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Exact and approximate estimation for maximum instantaneous current of CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution
EDTC '96 Proceedings of the 1996 European conference on Design and Test
EDTC '97 Proceedings of the 1997 European conference on Design and Test
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
Worst-case circuit delay taking into account power supply variations
Proceedings of the 41st annual Design Automation Conference
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Power estimation starategies for a low-power security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Stochastic variational analysis of large power grids considering intra-die correlations
Proceedings of the 43rd annual Design Automation Conference
RT-level vector selection for realistic peak power simulation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Precise identification of the worst-case voltage drop conditions in power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
Generating Worst-Case Stimuli for Accurate Power Grid Analysis
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Transition-aware decoupling-capacitor allocation in power noise reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sleep transistor sizing for leakage power minimization considering charge balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification and codesign of the package and die power delivery system using wavelets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sleep transistor sizing for leakage power minimization considering temporal correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast computation of discharge current upper bounds for clustered power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference on Computer-Aided Design
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Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits