Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Emerging power management tools for processor design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power distribution in high-performance design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
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This paper presents an input-independent method for finding bounds on the voltage drop in RC power bus in combinational macro-blocks circuits. The voltage at power bus nodes is expressed in term of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous high-to-low and low-to-high switching in a subinterval of a clock cycle. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes. The effects of signal statistical variations on the results are automatically included in our method. Comparisons to exhaustive HSPICE simulation of circuits extracted from layout are used to validate our approach.