Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Nosie and signal integrity in deep submicron design (panel)
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Current-driven wire planning for electromigration avoidance in analog circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Proceedings of the 2009 International Conference on Computer-Aided Design
A floorplan-based power network analysis methodology for system-on-chip designs
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hi-index | 0.01 |