Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Greedy wire-sizing is linear time
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An efficient technique for device and interconnect optimization in deep submicron designs
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A polynomial time optimal algorithm for simultaneous buffer and wire sizing
Proceedings of the conference on Design, automation and test in Europe
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Memory-efficient interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Line Testing Scheme for Clock's Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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