Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Perfect-balance planar clock routing with minimal path-length
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Clock tree synthesis for multi-chip modules
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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