IEEE Transactions on Computers
Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
A buffer distribution algorithm for high-performance clock net optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Associative skew clock routing for difficult instances
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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This paper presents a new problem formulation and algorithm of clockrouting combined with gate sizing for minimizing total logic andclock power. Instead of zero-skew or assuming a fixed skew bound, weseek to produce useful skews in clock routing. This is motivated bythe fact that only positive skew should beminimized while negative skew is useful in that itallows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clockand logic power(measured as a cost function) is minimized. Given a required clockperiod and feasible gate sizes, a set of negative and positive skewbounds are generated. The allowable skews within these bounds andfeasible gate sizes together form the feasible solution space of ourproblem. Inspired by the Deferred-Merge Embedding (DME) approach, wedevise a merging segment perturbation procedureto explore various tree configurations which result in correct clock operationunder the required period. Because of the large number of feasibleconfigurations, we adopt a simulated annealing approach to avoidbeing trapped in a local optimal configuration. This is complementedby a bi-partitioning heuristic to generate an appropriate connectiontopology to take advantage of useful skews. Experimental results ofour method have shown 12% to 20% total power reduction overprevious methods of clock routing with zero-skew or a single fixedskew bound and separately sizing logic gates. This is achieved at nosacrifice of clock frequency.