Introduction to algorithms
IEEE Transactions on Computers
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Clock network minimization methodology based on incremental placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Register placement for low power clock network
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Associative skew clock routing for difficult instances
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we propose new approaches for solving the useful-skew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for zero-skew tree [5; 1] and bounded-skew tree [8; 2] routings; hence, the names UST/DME and Greedy-UST/DME for our algorithms. They simultaneously perform skew scheduling and tree routing such that each local skew range is incrementally refined to a skew value that minimizes the wirelength during the bottom-up merging phase of DME. The resulting skew schedule is not only feasible, but is also best for routing in terms of wirelength. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total wirelength.