Computing optimal clock schedules

Resynthesis of multi-phase pipelines

DAC '93 Proceedings of the 30th international Design Automation Conference

TIM: a timing package for two-phase, level-clocked circuitry

DAC '93 Proceedings of the 30th international Design Automation Conference

Efficient implementation of retiming

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Optimization of critical paths in circuits with level-sensitive latches

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A timing analysis algorithm for circuits with level-sensitive latches

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

An algorithm for incremental timing analysis

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Optimal clock skew scheduling tolerant to process variations

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Clock skew optimization for ground bounce control

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Clock skew optimization for peak current reduction

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Clock Skew Optimization for Peak Current Reduction

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Verifying clock schedules

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Graph algorithms for clock schedule optimization

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Identification of critical paths in circuits with level-sensitive latches

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

The associative-skew clock routing problem

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Cycle time and slack optimization for VLSI-chips

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Clock skew scheduling for improved reliability via quadratic programming

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

UST/DME: a clock tree router for general skew constraints

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

UST/DME: a clock tree router for general skew constraints

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip

Discrete Applied Mathematics

Pushing ASIC performance in a power envelope

Proceedings of the 40th annual Design Automation Conference

On the performance of level-clocked circuits

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Functional clock schedule optimization

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock Scheduling and Clocktree Construction for High Performance ASICS

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Experimental analysis of the fastest optimum cycle ratio and mean algorithms

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Slack borrowing in flip-flop based sequential circuits

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Clock schedule verification under process variations

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Statistical Bellman-Ford algorithm with an application to retiming

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Effects of coupling capacitance and inductance on delay uncertainty and clock skew

Proceedings of the 44th annual Design Automation Conference

Computing the throughput of Concatenation State Machines

Journal of Discrete Algorithms

Binning optimization based on SSTA for transparently-latched circuits

Proceedings of the 2009 International Conference on Computer-Aided Design

Retiming: Theory and practice

Integration, the VLSI Journal