Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
IEEE Transactions on Computers
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Combinational logic optimization techniques in sequential logic synthesis
Combinational logic optimization techniques in sequential logic synthesis
Maximally fast and arbitrarily fast implementation of linear computations
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A zero-skew clock routing scheme for VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the temporal equivalence of sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Retiming with non-zero clock skew, variable register, and interconnect delay
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimal latch mapping and retiming within a tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retiming synchronous circuitry with imprecise delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal clock period FPGA technology mapping for sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming gated-clocks and precharged circuit structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance optimization of sequential circuits by eliminating retiming bottlenecks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Partitioning Sequential Circuits for Logic Optimization
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Efficient retiming under a general delay model
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Optimum retiming of large sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Decomposable searching problems and circuit optimization by retiming: two studies in general transformations of computational structures
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing optimization of multiphase sequential logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synchronous logic synthesis: algorithms for cycle-time minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the initial states of retimed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A task parallel algorithm for finding all-pairs shortest paths using the GPU
International Journal of High Performance Computing and Networking
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Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational portion of circuitry untouched. The central objective of retiming is to find a circuit with the minimum number of registers for a specified clock period. There are two common variants of this theme; minimizing the clock period without regard to the number of registers in the final circuit or minimizing the number of registers in the final circuit with no constraints on the clock period. Over a decade has elapsed since Leiserson and Saxe first presented a theoretical formulation to solve this problem for single-clock edge-triggered sequential circuits. The proposed algorithms have polynomial complexity. Since then research efforts have focussed on incorporating retiming in a synthesis framework, addressing issues that arise due to retiming, and extending the domain of circuits for which retiming can be applied. This paper presents a survey of retiming as it evolved from a theoretical formulation to a powerful optimization technique available in commercial tools. The issues that arise for a practical implementation of the basic retiming formulation are discussed. Some of the relevant research issues and key contributions are presented.