Optimum retiming of large sequential circuits

• Authors: S. T. Chakradhar
• Venue: VLSID '95 Proceedings of the 8th International Conference on VLSI Design
• Year: 1995

We present a new, fast algorithm for optimally retiming large sequential circuits under the unit delay model. Our method consists of two main steps: (1) computation of the optimum clock period and (2) computation of a feasible retiming For the optimum clock period. We construct a path graph that has as many vertices as there are flip-flops in the circuit. The path graph also has an additional vertex that corresponds to all primary Inputs and outputs of the circuit. There is an arc from a vertex to another if there is a strictly combinational path between the corresponding flip-flops, primary inputs or outputs. We formulate an integer linear program (ILP) on the path graph to compute the minimum clock period /spl phi//sub opt/ for which the path graph has no critical cycles. An optimum solution to the ILP is determined from the optimum solution of the corresponding linear program (LP) relaxation. We show that /spl phi//sub opt/ is also the optimum clock period for the circuit. After determining the optimum clock period, a feasible retiming for the optimum clock period is obtained using known retiming methods. Experimental results on several large benchmarks and production VLSI circuits show that our method is significantly faster than the best optimal retiming method known to date. Also, optimum retiming results for these benchmark circuits are being presented for the first time.