Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Optimum retiming of large sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
On the Properties of Irredundant Logic Networks
IEEE Transactions on Computers
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
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Retiming is used to optimize logic and improve the speed of operation in sequential circuits keeping the circuit behavior unchanged. In this paper, we show with various examples that retiming affects redundancy of faults. It may change an operationally redundant fault to a partially one, and a combinationally redundant fault to an irredundant but sequentially untestable fault. Many novel transformations of combinational redundancy to sequential redundancies are also exemplified. Thus, retiming strongly influences test generation and design for testability techniques in sequential circuits.