Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
EDTC '95 Proceedings of the 1995 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Synthesis of Sequential Circuits by Redundancy Removal and Retiming
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Partial Scan with Preselected Scan Signals
IEEE Transactions on Computers
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of synchronous circuits
Logic Synthesis and Verification
Verifying the correctness of FPGA logic synthesis algorithms
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Testability Implications of Performance-Driven Logic Synthesis
IEEE Design & Test
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Does retiming affect redundancy in sequential circuits?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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