DAC '93 Proceedings of the 30th international Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Resynthesis for sequential circuits designed with a specified initial state
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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In this paper we propose a method for synthesizing sequentialcircuits to reduce the number of gates and flip-flops by removingboth combinationally and sequentially redundant faults. In order toremove sequentially redundant faults these faults are converted intocombinationally redundant faults by using retiming techniques and thecombinationally redundant faults can be removed by using a testpattern generation method for combinational circuits. To simplify agiven circuit retiming is utilized for two purposes in thismethod. One is to find sequentially redundant faults and another is toreduce the number of flip-flops and gates. Before and after eachretiming the combinationally redundant faults are removed.Experimental results for ISCAS ‘89 benchmark circuits show that thismethod can remove many of sequentially redundant faults and canreduce a large number of gates and flip-flops.