Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Sequential Redundancy Identification Using Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Synthesis of Sequential Circuits by Redundancy Removal and Retiming
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
Functional broadside tests under an expanded definition of functional operation conditions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed. Specifically, their state diagrams have a strongly connected component that contains all the synchronization states. This strongly connected component, called the main strongly-connected component, is reachable from all other strongly connected components. In addition to redundant faults that can always be removed, we show that there are two types of partially detectable faults in circuits that have synchronizing sequences. In the presence of the first type of faults, the circuit becomes unsynchronizable. Signal lines carrying such faults cannot be removed. The other type of partially detectable faults leave the circuit synchronizable. We show that such faults do not affect the main strongly connected component, and hence the corresponding signal lines can be removed without affecting the operation of the circuit after it is synchronized. We also define weakly synchronizable circuits acid derive similar results regarding the removal of redundant logic in them. The class of removable lines is thus extended beyond those corresponding to redundant faults to include some partially detectable faults as well. We present experimental evidence to the existence of partially detectable faults that correspond to signal lines that can be removed in benchmark circuits