Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Model checking
A machine program for theorem-proving
Communications of the ACM
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
Alignability equivalence of synchronous sequential circuits
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Theory of safe replacements for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Design for verification in system-level models and RTL
Proceedings of the 44th annual Design Automation Conference
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
Functional Verification of Power Gated Designs by Compositional Reasoning
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Functional verification of power gated designs by compositional reasoning
Formal Methods in System Design
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
On formal equivalence verification of hardware
CSR'08 Proceedings of the 3rd international conference on Computer science: theory and applications
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
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We are interested in sequential hardware equivalence (or alignability equivalence) verification of synchronous sequential circuits as stated in C. Pixley (1992). To cope with large industrial designs, the circuits must be divided into smaller subcircuits and verified separately. Furthermore, in order to succeed in verifying the subcircuits, design constraints must be added to the subcircuits. These constraints mimic "essential" behavior of the subcircuit environment. In this work, we extend the classical alignability theory in the presence of design constraints, and prove a compositionality result allowing inferring alignability of the circuits from alignability of the subcircuits. As a result, we build a divide and conquer framework for alignability verification. This framework is successfully used on Intel designs.