AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Alignability equivalence of synchronous sequential circuits
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Post-reboot Equivalence and Compositional Verification of Hardware
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Theory of safe replacements for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
On formal equivalence verification of hardware
CSR'08 Proceedings of the 3rd international conference on Computer science: theory and applications
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
Proceedings of the 50th Annual Design Automation Conference
Hi-index | 0.00 |
As the pressure to produce smaller and faster designs increases, the need for formal verification of sequential transformations increases proportionally. In this paper we describe a framework that attempts to extend the set of designs that can be equivalence checked. Our focus lies in integrating sequential equivalence checking into a standard design flow that relies on combinational equivalence checking today. In order to do so, we can not make use of reset state or reset sequence information (as this is not given in combinational equivalence checking), and we need to mitigate the complexity inherent in the traditional sequential equivalence checking algorithms. Our solution integrates combinational and sequential equivalence checking in such a way that the individual analyses benefit from each other. The experimental results show that our framework can verify designs which are out of range for pure sequential equivalence checking methods aimed designs with unknown reset states.