Proceedings of the conference on Design, automation and test in Europe
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
On formal equivalence verification of hardware
CSR'08 Proceedings of the 3rd international conference on Computer science: theory and applications
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We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combinational equivalence verification of hardware, the way it was performed over the years in the industry. We define a concept of post-reboot bisimulation, which better suits the Hardware Machines, and show that a right form of combinational equivalence is in fact a form of post-reboot bisimulation. Further, we show that alignability equivalence is a form of post-reboot bisimulation, too, and the latter is a refinement of alignability in the context of compositional hardware verification. We find that post-reboot bisimulation has important advantages over alignability also in the wider context of formal hardware verification, where equivalence verification is combined with formal property verification and with validation of a reboot sequence. As a result, we propose a more comprehensive, compositional, and fullyformal framework for hardware verification. Our results are extendible to other forms of labeled transition systems and adaptable to other forms of bisimulation used to model and verify complex hardware and software systems.