Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Post-reboot Equivalence and Compositional Verification of Hardware
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Sequential equivalence checking based on k-th invariants and circuit SAT solving
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Memory modeling in ESL-RTL equivalence checking
Proceedings of the 44th annual Design Automation Conference
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Construction of concrete verification models from C++
Proceedings of the 45th annual Design Automation Conference
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
System verification of concurrent RTL modules by compositional path predicate abstraction
Proceedings of the 49th Annual Design Automation Conference
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
Microprocessors & Microsystems
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We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a system-level model versus an RTL design which has been derived from the former either manually or through high-level synthesis. The existing state-of-the-art in formal verification/SEC does not provide an efficient mechanism to perform such an equivalence check. Our technique reduces the SEC problem to a cycle-accurate equivalence-checking problem by constructing a pair of normalized cycle-accurate designs from the original designs, on which standard equivalence-checking techniques can then be deployed. We report the results of deploying our techniques on several industrial examples.