Synthesis of VLSI designs with symbolic techniques
Synthesis of VLSI designs with symbolic techniques
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Latch Redundancy Removal Without Global Reset
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
The Verifiacation Problem for Safe Replaceability
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Design replacements for sequential circuits
Design replacements for sequential circuits
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Theory of safe replacements for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
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We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the existence of a hardware reset line and consequently a fixed power-up state; in the absence of the same, a common premise is that the design's environment will apply an initializing sequence. We review the concept of safe replaceability which does away with these assumptions and the delay-safe replaceability notion, which is applicable when the design's output is not used for a certain number of cycles after power-up. We then develop procedures for optimizing the combinational next-state and output logic, as well as routines for reencoding the state space and removing state bits under these replaceability criteria. Experimental results demonstrate the effectiveness of our algorithms.