Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Binary decision diagrams and their applications to implicit enumeration techniques in logic synthesis
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Verifiacation Problem for Safe Replaceability
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Formula-Dependent Equivalence for Compositional CTL Model Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Functional broadside tests under an expanded definition of functional operation conditions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |