Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Control optimization based on resynchronization of operations
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Don't care set specifications in combinational and synchronous logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-level synthesis for safe replaceability
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Permissible observability relations in FSM networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Input don't care sequences in FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Using combinational verification for sequential circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification
Sequential Permissible Functions and their Application to Circuit Optimization
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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