Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Input Don''t Care Sequences
Exact and heuristic algorithms for the minimization of incompletely specified state machines
EURO-DAC '91 Proceedings of the conference on European design automation
Permissible observability relations in FSM networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
A fully implicit algorithm for exact state minimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequential synthesis using S1S
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization of FSM networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Symbolic optimization of FSM networks based on sequential ATPG techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Environment modeling and language universality
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
Optimization of synchronous circuits
Logic Synthesis and Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the use of reset to increase the testability of interconnected finite-state machines
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Testing in context: framework and test derivation
Computer Communications
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