Programming and verifying critical systems by means of the synchronous data-flow language LUSTRE
SIGSOFT '91 Proceedings of the conference on Software for citical systems
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Programming and Verifying Real-Time Systems by Means of the Synchronous Data-Flow Language LUSTRE
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
Maximal reduction of lookup-table based FPGAs
EURO-DAC '92 Proceedings of the conference on European design automation
Finite state machine verification on MIMD machines
EURO-DAC '92 Proceedings of the conference on European design automation
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
On computing the transitive closure of a state transition relation
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
Universal logic gate for FPGA design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
On the computation of the set of reachable states of hybrid models
DAC '94 Proceedings of the 31st annual Design Automation Conference
Permissible observability relations in FSM networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems
EURO-DAC '94 Proceedings of the conference on European design automation
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multi-level logic optimization of FSM networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
State reduction using reversible rules
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic model checking for event-driven real-time systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Computing the observable equivalence relation of a finite state machine
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Representation and symbolic manipulation of linearly inductive Boolean functions
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Input don't care sequences in FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Safe BDD minimization using don't cares
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Don't care-based BDD minimization for embedded software
DAC '98 Proceedings of the 35th annual Design Automation Conference
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Waiting false path analysis of sequential logic circuits for performance optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The General Product Machine: a New Model for Symbolic FSM Traversal
Formal Methods in System Design
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decoupling synchronization from local control for efficient symbolic model checking of statecharts
Proceedings of the 21st international conference on Software engineering
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust techniques for watermarking sequential circuit designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Non-stationary effects in trace-driven power analysis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
Distance driven finite state machine traversal
Proceedings of the 37th Annual Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
A VHDL error simulator for functional test generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Methods in System Design
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
Multi-clock path analysis using propositional satisfiability
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A new partitioning scheme for improvement of image computation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis
Formal Methods in System Design
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Ordered binary decision diagrams
Logic Synthesis and Verification
Data structures for Boolean functions
Computational Discrete Mathematics
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Validation of Synchronous Reactive Systems: From Formal Verification to Automatic Testing
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Compositional Reasoning in Model Checking
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Progress on the State Explosion Problem in Model Checking
Informatics - 10 Years Back. 10 Years Ahead.
Distributed Symbolic Model Checking for µ-Calculus
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Model Checking: Historical Perspective and Example (Extended Abstract)
TABLEAUX '98 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
Quasi-algebraic decompositions of switching functions
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
An Efficient Algorithm for Real-Time Symbolic Model Checking
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formal Methods in System Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Verification of synthesized circuits at register transfer level with flow graphs
EURO-DAC '91 Proceedings of the conference on European design automation
Abstraction of assembler programs for symbolic worst case execution time analysis
Proceedings of the 41st annual Design Automation Conference
Encyclopedia of Computer Science
Distributed Symbolic Model Checking for μ-Calculus
Formal Methods in System Design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Regression for Classical and Nondeterministic Planning
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
Syntax-driven reachable state space construction of synchronous reactive programs
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Abstract property language for MDG model checking methodology
International Journal of Computer Applications in Technology
Fast submatch extraction using OBDDs
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Verification and enforcement of access control policies
Formal Methods in System Design
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