NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Logic optimization by an improved sequential redundancy addition and removal techniques
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Incremental re-encoding for symbolic traversal of product machines
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Computing the observable equivalence relation of a finite state machine
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A symbolic algorithm for maximum flow in 0-1 networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The General Product Machine: a New Model for Symbolic FSM Traversal
Formal Methods in System Design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient State Space Pruning in Symbolic Backward Traversal
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
The Backward Walk Approach in FSM Verification
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
| Hi-index | 0.00 |
Design tools for embedded reactive systems commonly use a model of computation that employs both synchronous and asynchronous communication styles. We form a junction between these two with an implementation of synchronous languages and circuits (Esterel) ...