Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
Intellectual property protection by watermarking combinational logic synthesis solutions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reencoding for cycle-time minimization under fixed encoding length
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Factoring logic functions using graph partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On using satisfiability-based pruning techniques in covering algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
OBDD Minimization Based on Two-Level Representation of Boolean Functions
IEEE Transactions on Computers
Formal Methods in System Design
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The HSSM macro-architecture, Virtual Machine and H languages
ACM SIGPLAN Notices
Transformation rules for designing CNOT-based quantum circuits
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Multi-level logic optimization
Logic Synthesis and Verification
Logical and physical design: a flow perspective
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Compressing inverted files in scalable information systems by binary decision diagram encoding
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Generalized symmetries in boolean functions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
BOOM: a heuristic boolean minimizer
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
Verifying the correctness of FPGA logic synthesis algorithms
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Flexibility/cost-tradeoffs of platform-based systems
Embedded processor design challenges
Conflict driven learning in a quantified Boolean Satisfiability solver
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An arbitrary twoqubit computation In 23 elementary gates or less
Proceedings of the 40th annual Design Automation Conference
Automated deduction for many-valued logics
Handbook of automated reasoning
Systems Analysis Modelling Simulation
Concrete Impact of Formal Verification on Quality in IP Design and Implementation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
On-Line Monitor Design of Finite-State Machines
Journal of Electronic Testing: Theory and Applications
Transformation rules for CNOT-based quantum circuits and their applications
New Generation Computing - Quantum computing
Satisfiability-Based Algorithms for Boolean Optimization
Annals of Mathematics and Artificial Intelligence
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System-on-chip validation using UML and CWL
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Utilizing don't care states in SAT-based bounded sequential problems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Effective bounding techniques for solving unate and binate covering problems
Proceedings of the 42nd annual Design Automation Conference
Encyclopedia of Computer Science
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Factoring boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Debugging sequential circuits using Boolean satisfiability
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An anytime symmetry detection algorithm for ROBDDs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On N-Detect Pattern Set Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling component connectors in Reo by constraint automata
Science of Computer Programming - Special issue on second international workshop on foundations of coordination languages and software architectures (FOCLASA'03)
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lower bounds on the OBDD size of two fundamental functions' graphs
Information Processing Letters
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Symbolic Model Checking for Channel-based Component Connectors
Electronic Notes in Theoretical Computer Science (ENTCS)
High-contrast algorithm behavior: observation, hypothesis, and experimental design
Proceedings of the 2007 workshop on Experimental computer science
Performance testing of combinatorial solvers with isomorph class instances
Proceedings of the 2007 workshop on Experimental computer science
High-contrast algorithm behavior: observation, conjecture, and experimental design
ecs'07 Experimental computer science on Experimental computer science
Performance testing of combinatorial solvers with isomorph class instances
ecs'07 Experimental computer science on Experimental computer science
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimization of decision trees is hard to approximate
Journal of Computer and System Sciences
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Protecting bus-based hardware IP by secret sharing
Proceedings of the 45th annual Design Automation Conference
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Proceedings of the conference on Design, automation and test in Europe
EPIC: ending piracy of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
On analysis and synthesis of (n, k)-non-linear feedback shift registers
Proceedings of the conference on Design, automation and test in Europe
Note: Minimization of circuit registers: Retiming revisited
Discrete Applied Mathematics
A Computational Scheme Based on Random Boolean Networks
Transactions on Computational Systems Biology X
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PolyBoRi: A framework for Gröbner-basis computations with Boolean polynomials
Journal of Symbolic Computation
Symbolic model checking for channel-based component connectors
Science of Computer Programming
Thermal sensor allocation and placement for reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
Factoring Boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Symbolic Reasoning with Weighted and Normalized Decision Diagrams
Electronic Notes in Theoretical Computer Science (ENTCS)
Modelling of complex systems given as a mealy machine with linear decision diagrams
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartII
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Branching vs. linear time: semantical perspective
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Static slicing-based pre-reduction technique for MDG model-checker
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experimental evaluation of classical automata constructions
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Journal of Computer and System Sciences
The complexity of problems on implicitly represented inputs
SOFSEM'06 Proceedings of the 32nd conference on Current Trends in Theory and Practice of Computer Science
On subsumption removal and on-the-fly CNF simplification
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Lower bounds on the OBDD size of graphs of some popular functions
SOFSEM'05 Proceedings of the 31st international conference on Theory and Practice of Computer Science
Bi-decomposition of large Boolean functions using blocking edge graphs
Proceedings of the International Conference on Computer-Aided Design
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Genetic algorithms for the variable ordering problem of binary decision diagrams
FOGA'05 Proceedings of the 8th international conference on Foundations of Genetic Algorithms
On symbolic scheduling independent tasks with restricted execution times
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
A symbolic approach to the all-pairs shortest-paths problem
WG'04 Proceedings of the 30th international conference on Graph-Theoretic Concepts in Computer Science
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Exponential lower bounds on the space complexity of OBDD-Based graph algorithms
LATIN'06 Proceedings of the 7th Latin American conference on Theoretical Informatics
A special class of fuzzified normal forms
ICIC'11 Proceedings of the 7th international conference on Intelligent Computing: bio-inspired computing and applications
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo
Proceedings of the International Conference on Computer-Aided Design
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
Dynamic behavior of cell signaling networks: model design and analysis automation
Proceedings of the 50th Annual Design Automation Conference
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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From the Publisher:Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebra, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles. Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study. Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.